Integrated circuit structures typically include a number of input/output (I/O) pads that facilitate electrical connection of the integrated circuit to external devices. One widely used electrical connection technique is wire bonding, which involves thermosonically bonding a thin gold (Au) or copper (Cu) wire to the I/O pad (often referred to as a “bond pad”).
FIG. 1 shows a cross-section of a standard bond pad stack 100. The bond pad stack 100 includes a number of aluminum (Al) or Cu metallization layers, layers M1-M4 in this case, that are separated from one another by inner dielectric (ILD) material 102, typically deposited silicon dioxide (SiO2). In order to connect the various metallization layers M1-M4, conductive vias 104 are often formed beneath the bond pad to provide desired circuit characteristics. A layer of passivation material 106, typically silicon nitride, is formed over the top metallization layer, layer M4 in this case, and patterned to expose an upper surface area 108 of the M4 layer to serve as a bond pad.
Conventional wire bonding techniques impart a significant amount of stress to the standard bond pad design, often resulting in cracks in the inner layer (ILD) that underlies the bond pads. These cracks tend to propagate through the circuit structure and can cause current leakage and/or performance degradation.
Because of the problems that may be caused by wire bonding, it is common to avoid placing active circuit elements in regions of the integrated circuit die that are directly below the bond pads. While this helps reduce the risk of cracking, since the bond pads occupy a significant percentage if the total surface are of the die, prohibiting placement of active circuits beneath the bond pads results in an undesirable increase in die size. Also, while in the past there have typically been three or four metal layers overlying the active circuit elements in the bond pad area, it is desirable in an increasing number of circuit applications to have the flexibility to place active circuitry directly beneath the bond pad.
FIG. 2 shows a known bond pad stack design 200 intended to address the above-discussed issues. The bond pad stack design 200 includes a layer of inner layer dielectric (ILD) 202, e.g., silicon nitride, formed over active circuitry 204. An upper metal layer 206 is formed on the ILD 202. Rather than providing for wire bonding directly to bond pads of the upper metal layer, as in the case of the standard FIG. 1 bond pad stack, the bond pad stack design 200 provides an extra passivation nitride layer 208 over the upper metal layer 206. A layer of metal, e.g., aluminum (Al) or copper (Cu), is then formed and patterned to provide bond pads 210 on the extra passivation layer.
While the FIG. 2 bond pad stack 200 provides a more robust design than the FIG. 1 standard bond pad stack 100, thereby enhancing the viability of under bond pad active circuitry, its implementation requires an additional mask layer and increases cost and cycle time.